Direct digital frequency synthesizers with polynomial hyperfolding technique

A new approach to design the phase to sine mapper of a direct digital frequency synthesizer (DDFS) is presented. The proposed technique uses an optimized polynomial expansion of sine and cosine functions to achieve either a 60-dBc spurious free dynamic range (SFDR), with a second-order polynomial, o...

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Bibliographic Details
Published in:IEEE transactions on circuits and systems. 2, Analog and digital signal processing Analog and digital signal processing, 2004-07, Vol.51 (7), p.337-344
Main Authors: De Caro, D., Napoli, E., Strollo, A.G.M.
Format: Article
Language:English
Subjects:
Algorithm design and analysis
Circuits
Computation
Computer architecture
Design engineering
Digital
Dynamic range
Dynamical systems
Frequency control
Frequency synthesizers
Hardware
Mathematical analysis
Polynomials
Read only memory
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Summary:A new approach to design the phase to sine mapper of a direct digital frequency synthesizer (DDFS) is presented. The proposed technique uses an optimized polynomial expansion of sine and cosine functions to achieve either a 60-dBc spurious free dynamic range (SFDR), with a second-order polynomial, or a 80-dBc SFDR, with third-order polynomials. Polynomial computation is done by using new canonical-signed-digit (CSD) hyperfolding technique. This approach exploits all the symmetries of polynomials parallel computation and uses CSD encoding to minimize hardware complexity. CSD hyperfolding technique is also presented in the paper. The performances of new DDFS compares favorably with circuits designed using state-of-the-art Cordic algorithm technique.
ISSN:1549-7747
1057-7130
1558-3791
DOI:10.1109/TCSII.2004.829553