A 210-mW graphics LSI implementing full 3-D pipeline with 264 mtexels/s texturing for mobile multimedia applications

• Published in: IEEE journal of solid-state circuits 2004-02, Vol.39 (2), p.358-367
• Main Authors: Woo, R., Choi, S., Sohn, J.-H., Song, S.-J., Yoo, H.-J.
• Format: Article
• Language: English
• Subjects: Chips; Clocks; Dynamic random access memory; Engines; Filtering; Graphics; Large scale integration; Logic; MPEG 4 Standard; Pipelines; Random access memory; Reduced instruction set computing; Rendering; Rendering (computer graphics); RISC processors; Special effects; Two dimensional displays
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2003.821781

A 121-mm/sup 2/ graphics LSI is designed and implemented for portable two-dimensional (2-D) and three-dimensional (3-D) graphics and MPEG-4 applications. The LSI contains a RISC processor with a multiply-accumulate unit (MAC), a 3-D rendering engine, a programmable power optimizer, and 29-Mb embedded DRAM. The chip is built in a 0.16-/spl mu/m pure DRAM technology to reduce the fabrication cost. Texture-mapped 3-D graphics with perspective-correct address calculation and bilinear MIPMAP filtering can be realized while consuming the low power with the help of depth-first clock gating, address alignment logic, and embedded DRAM. Programmable clocking allows the LSI to operate in lower power modes for various applications. The chip consumes less than 210 mW, delivering 66 Mpixels/s and 264 Mtexel/s texture-mapped pixels with real-time special effects such as full-scene antialiasing and motion blur.