Hierarchical Design of an Application-Specific Instruction Set Processor for High-Throughput and Scalable FFT Processing

• Published in: IEEE transactions on very large scale integration (VLSI) systems 2012-03, Vol.20 (3), p.551-563
• Main Authors: Guan, Xuan, Fei, Yunsi, Lin, Hai
• Format: Article
• Language: English
• Subjects: Algorithm design and analysis; Application-specific instruction set processor (ASIP); Applied sciences; Arrays; Circuit properties; Communication systems; Computation; Data processing; Design engineering; Design. Technologies. Operation analysis. Testing; Digital circuits; Digital signal processing; Electric, optical and optoelectronic circuits; Electronic circuits; Electronics; Exact sciences and technology; fast Fourier transform (FFT); Field programmable gate arrays; Hardware; hierarchical design; Integrated circuits; Integrated circuits by function (including memories and processors); Microprocessors; processor architecture; Registers; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Throughput; Very large scale integration; Wireless communications
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2011.2105512

Fast Fourier transformation (FFT), a kernel data processing task in communication systems, has been studied intensively for efficient software and hardware implementations. Nowadays, various orthogonal frequency division multiplexing (OFDM)-based wireless communication standards have raised more stringent requirements on both throughput and flexibility for FFT computation. Application-specific instruction set processor (ASIP) has emerged as a promising solution to meet these requirements. This paper presents a novel hierarchical design of an ASIP tailored for FFT. We reconstruct the FFT computation flow into a scalable array structure based on an 8-point butterfly unit (BU). The array structure can easily expand along both the horizontal and vertical dimensions for any-point FFT computation. We incorporate custom register files to reduce memory access and derive a regular data addressing rule accordingly. With the microarchitecture modifications, we extend the instruction set architecture (ISA) with new instructions to accelerate FFT operations. An FFT ASIP is implemented on Tensilica's reconfigurable processor platform. Our FFT ASIP achieves the data throughput of 405.7 Mb/s for 1 K-point FFT, which attains UWB-OFDM specifications. The area of our custom processor is 147 kilo gates and the total processor power consumption is 60.7 mW, which are acceptable compared to several other designs such as application specific integrated circuit, digital signal processing, field-programmable gate array, and other ASIP implementations. We also extend the implementation for up to 8 K-point FFTs, with degraded performance but still meeting the requirements of those communications standards that demand large-size FFT computations.