40-43-Gb/s OC-768 16:1 MUX/CMU chipset with SFI-5 compliance

• Published in: IEEE journal of solid-state circuits 2003-12, Vol.38 (12), p.2169-2180
• Main Authors: Hai Tao, Shaeffer, D.K., Min Xu, Benyamin, S., Condito, V., Kudszus, S., Qinghung Lee, Ong, A., Shahani, A., Xiaomin Si, Wong, W., Tarsia, M.
• Format: Article
• Language: English
• Subjects: Architecture; Chips (electronics); Clocks; Design engineering; Germanium silicon alloys; High speed optical techniques; Jitter; Multiplexing; Optical network units; Optical noise; Partitioning; Semiconductor device measurement; Silicon germanides; Silicon germanium; SONET; Time measurements
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2003.818575

In this paper, we present two copackaged ICs that provide complete OC-768 16:1 multiplexer (MUX) and clock multiplying unit (CMU) functionality. The 17-input 2.5-2.68-Gb/s parallel interface is Serdes Framer Interface Level 5 (SFI-5) compliant while the 40-43-Gb/s output satisfies OC-768 jitter generation specifications with 7 dB of margin. The system architecture and two-chip partitioning are discussed, followed by descriptions of the design challenges including SFI-5 compliance, 40-Gb/s MUX timing, and 20-GHz clock generation. A novel technique for stabilizing timing margins in the final high-speed multiplexer stage using in-phase and quadrature clocks is also presented. This chipset accommodates 11 bits of static skew and 21 bits of dynamic wander at the SFI-5 interface, while generating 125 fs rms of random jitter and 3.1 ps peak-to-peak of deterministic jitter at its 40-43-Gb/s outputs. The measured bit-error ratio is less than 10/sup -15/ for 2/sup 31/-1 PRBS data and is measurement time limited. The two chips occupy 15.6 mm/sup 2/ and 8.25 mm/sup 2/ of die area. Both are implemented in a 120-GHz f/sub T/ SiGe BiCMOS process.