A high-performance and low-power 32-bit multiply-accumulate unit with single-instruction-multiple-data (SIMD) feature

A high-performance and low-power 32-bit multiply-accumulate unit (MAC) is described in this paper. The last mixed-length encoding scheme used in the MAC leverages the advantage of a 16-bit encoding scheme without adding extra delay to the faster four-stage Wallace tree of a 12-bit encoding scheme. W...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 2002-07, Vol.37 (7), p.926-931
Main Authors: Yuyun Liao, Roberts, D.B.
Format: Article
Language:English
Subjects:
Circuits
CMOS
CMOS logic circuits
Delay
Digital signal processing
Encoding
Frequency
Handles
High speed
Logic
Microarchitecture
Microprocessors
Pipelines
Reduced instruction set computing
Streaming media
Streams
Throughput
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Summary:A high-performance and low-power 32-bit multiply-accumulate unit (MAC) is described in this paper. The last mixed-length encoding scheme used in the MAC leverages the advantage of a 16-bit encoding scheme without adding extra delay to the faster four-stage Wallace tree of a 12-bit encoding scheme. With this new encoding scheme, one-cycle throughput for 16-bit /spl times/16-bit and 32-bit /spl times/16-bit MAC instructions was achieved at very high frequencies. To handle media streams more efficiently, the single-instruction-multiple-data (SIMD) and the multiply-with-implicit-accumulate (MIA) features were added. A mixture of static CMOS logic and complementary pass-gate logic (CPL) was used to achieve the high-speed and low-power goals. Several power-saving techniques were also implemented in this MAC.
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2002.1015692