A novel simplified process for fabricating a very high density p-channel trench gate power MOSFET

A novel simplified fabrication method of a very high density p-channel trench gate power MOSFET using four mask layers and nitride/TEOS sidewall spacers is realized. The proposed process showed improved on-resistance characteristics of the device with increasing cell density and the cost-effective p...

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Bibliographic Details
Published in:IEEE electron device letters 2000-07, Vol.21 (7), p.365-367
Main Authors: Nam, Kee Soo, Lee, Ju Wook, Kim, Sang-Gi, Roh, Tae Moon, Park, Hoon Soo, Koo, Jin Gun, Cho, Kyung Ik
Format: Article
Language:English
Subjects:
Battery management systems
Conductivity
Density
Devices
Electric potential
Etching
Fabrication
Gates
High density
Materials science and technology
Moon
MOSFET circuits
MOSFETs
Power MOSFET
Production
Silicon
Trenches
Voltage
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Summary:A novel simplified fabrication method of a very high density p-channel trench gate power MOSFET using four mask layers and nitride/TEOS sidewall spacers is realized. The proposed process showed improved on-resistance characteristics of the device with increasing cell density and the cost-effective production capability due to the lesser number of processing steps. By using this process technique, a remarkably increased high density (100 Mcell/inch 2 ) trench gate power MOSFET with a cell pitch of 2.5 μm could be effectively realized. The fabricated device had a low specific on-resistance of 1.1 m/spl Omega/-cm 2 with a breakdown voltage of -36 V.
ISSN:0741-3106
1558-0563
DOI:10.1109/55.847382