On-chip system level protection of FM antenna pin with improved linearity

An on-chip protection against IEC 61000-4-2 discharges is presented. The protection level is tested by means of HMM stress. The failure signature is identified by means of TLP testing and physical failure analysis. It is shown that it is possible to accurately predict the HMM failure level by means...

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Bibliographic Details
Published in:Microelectronics and reliability 2011-12, Vol.51 (12), p.2129-2136
Main Authors: Notermans, Guido, Maksimovic, Dejan, Vermont, Gerd, Maasakkers, Michiel van, Pusa, Fredrik, Smedes, Theo
Format: Article
Language:English
Subjects:
Antennas
Applied sciences
Calibration
Circuits
Electronics
Exact sciences and technology
Failure
Failure analysis
Linearity
Mathematical models
Signatures
Testing, measurement, noise and reliability
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Summary:An on-chip protection against IEC 61000-4-2 discharges is presented. The protection level is tested by means of HMM stress. The failure signature is identified by means of TLP testing and physical failure analysis. It is shown that it is possible to accurately predict the HMM failure level by means of a simplified circuit model, calibrated by means of 100 ns TLP data. A second version of the on-chip protection combines an improved linearity of the FM output with a superior ESD performance.
ISSN:0026-2714
1872-941X
DOI:10.1016/j.microrel.2011.05.018