Technique for Template Generation for Simultaneous Testing of Multiple Identical Functional Units in Super-scalar Architecture

At-speed testing has emerged as dominant test requirement in the era of high speed microprocessors. Since the conventional testing techniques prove to be incompetent, Instruction-Based Self-Testing (IBST) has been proposed as an effective alternate to those conventional techniques for at-speed testi...

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Bibliographic Details
Published in:International journal of computer applications 2011-01, Vol.34 (8)
Main Authors: Choudhary, Rahul Raj, Sinsinwar, Gayaprasad, Kajala, Aditi, Bhardwaj, Pooja
Format: Article
Language:English
Subjects:
Architecture
Delay
Digital systems
Faults
High speed
Mathematical analysis
Microprocessors
Vectors (mathematics)
Online Access:Get full text
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Summary:At-speed testing has emerged as dominant test requirement in the era of high speed microprocessors. Since the conventional testing techniques prove to be incompetent, Instruction-Based Self-Testing (IBST) has been proposed as an effective alternate to those conventional techniques for at-speed testing of high performance microprocessors. The Superscalar architectures, with vast functionality and exceptionally high speed have become the central integral part of modern high speed digital systems. However, testing superscalar microprocessors using this approach faces serious challenges, due to the out-of-order execution with multiple functional units and in-order commit behaviour. This paper discusses the test program generation procedure (template based) for multiple identical functional units in a superscalar architecture. Procedures for delay fault testing, which make sure that generated test vectors are applied in the correct order to test each testable path, are developed. The preliminary work has been presented in EWDTS[1]
ISSN:0975-8887
0975-8887
DOI:10.5120/4122-5843