A 5-Gbit/s Clock- and Data-Recovery Circuit With 1/8-Rate Linear Phase Detector in 0.18- rm mu hbox m CMOS Technology

With a new 1/8-rate linear phase detector (PD), a 5-Gbit/s clock and data recovery (CDR) circuit is implemented in a digital 0.18-mum CMOS technology. The outputs of the PD have much wider pulse than those of the conventional linear PDs. Thus, the design of circuits such as the PD and charge becomes...

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Bibliographic Details
Published in:IEEE transactions on circuits and systems. II, Express briefs Express briefs, 2009-01, Vol.56 (1)
Main Authors: Seo, Young-Suk, Lee, Jang-Woo, Kim, Hong-Jung, Yoo, Changsik, Lee, Jae-Jin, Jeong, Chun-Seok
Format: Article
Language:English
Subjects:
Circuits
Clocks
CMOS
Design engineering
Detectors
Jitter
Linear phase
Pseudorandom
Online Access:Get full text
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Summary:With a new 1/8-rate linear phase detector (PD), a 5-Gbit/s clock and data recovery (CDR) circuit is implemented in a digital 0.18-mum CMOS technology. The outputs of the PD have much wider pulse than those of the conventional linear PDs. Thus, the design of circuits such as the PD and charge becomes much easier, and the maximum data rate is no longer limited by the speed of phase detection. The CDR shows 6.8-ps rms and 57.4-ps peak-to-peak jitter in the recovered clock and 10 super(-12) bit error rate for 2 super(31)-1 pseudorandom binary-sequence input while consuming 144 mW from a 1.8-V supply.
ISSN:1549-7747
DOI:10.1109/TCSII.2008.2008520