Area and speed oriented synthesis of FSMs for PAL-based CPLDs

► Technology-mapping of FSM for CPLD. ► State assignment with two-level minimization for area or speed oriented synthesis. ► Area optimization based on the graph of outputs. ► Speed minimization by means of tri-state buffers. New two-step methods of FSMs synthesis for PAL-based CPLDs are presented i...

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Bibliographic Details
Published in:Microprocessors and microsystems 2012-02, Vol.36 (1), p.45-61
Main Authors: Czerwinski, R., Kania, D.
Format: Article
Language:English
Subjects:
Blocking
Buffers
CPLD
FSM
Logic optimization
Logic synthesis
Maximization
Microprocessors
Minimization
Optimization
Programmable logic devices
State assignment
Synthesis
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Summary:► Technology-mapping of FSM for CPLD. ► State assignment with two-level minimization for area or speed oriented synthesis. ► Area optimization based on the graph of outputs. ► Speed minimization by means of tri-state buffers. New two-step methods of FSMs synthesis for PAL-based CPLDs are presented in the paper. The methods strive to find the optimum fit for a FSM to the structure of CPLD and aim at area and speed optimization. The first step for both methods is original state assignment that includes: techniques of two-level minimization, the limited number of terms contained in the cell and elements of adjusting to the logic optimization. The second step in the method oriented toward area minimization is PAL-oriented multi-level optimization, which is a search for implicants that can be shared by several functions. The second step in the method oriented toward speed maximization is based on utilizing tri-state buffers, thus enabling achievement of a one-logic-level output block.
ISSN:0141-9331
1872-9436
DOI:10.1016/j.micpro.2011.06.004