FPGA implementation of digital constant fraction algorithm with fractional delay for optimal time resolution

In a recent development of a fully digital spectrometer for time differential perturbed angular correlations a true constant fraction trigger (CFT) algorithm was implemented that, however, allowed for integer delays, i.e. integer multiples of the sampling interval, only. With a sampling rate of 1GS/...

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Bibliographic Details
Published in:Nuclear instruments & methods in physics research. Section A, Accelerators, spectrometers, detectors and associated equipment Accelerators, spectrometers, detectors and associated equipment, 2012-05, Vol.674, p.24-27
Main Authors: Jäger, Markus, Butz, Tilman
Format: Article
Language:English
Subjects:
Algorithms
Constant fraction
Delay
Digital
Digital sampling
Field programmable gate arrays
FPGA
Fractional delay
Integers
Optimization
Sampling
Spectrometers
Sub-ns timing
U1080A
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Summary:In a recent development of a fully digital spectrometer for time differential perturbed angular correlations a true constant fraction trigger (CFT) algorithm was implemented that, however, allowed for integer delays, i.e. integer multiples of the sampling interval, only. With a sampling rate of 1GS/s and BaF2 scintillators this turned out to be insufficient. Here, we present an extension of the algorithm to fractional delays implemented in field programmable gate arrays (FPGAs). Furthermore, we derive a criterion for the delay for optimum timing based on the steepest slope of the CFT signal. Experimental data are given for LaBr3(Ce) scintillators and 511keV–511keV prompt coincidences that corroborate the theoretical result.
ISSN:0168-9002
1872-9576
DOI:10.1016/j.nima.2012.01.022