Efficient Hardware Accelerators for the Computation of Tchebichef Moments

• Published in: IEEE transactions on circuits and systems for video technology 2012-03, Vol.22 (3), p.414-425
• Main Authors: Kah-Hyong Chang, Paramesran, R., Asli, B. H. S., Chern-Loon Lim
• Format: Article
• Language: English
• Subjects: Accelerator architectures; Accelerators; Algorithms; Applied sciences; Circuit properties; Clocks; Computation; Delay; Design engineering; Design. Technologies. Operation analysis. Testing; Detection, estimation, filtering, equalization, prediction; Digital filters; Electric, optical and optoelectronic circuits; Electronic circuits; Electronics; Exact sciences and technology; Frames; Frequency filters; Hardware; Information, signal and communications theory; Integrated circuits; large dynamic range; moment methods; Multiplexing; Multiplication; Pixels; Random access memory; Real time systems; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Signal and communications theory; Signal, noise; Spatial resolution; Studies; Telecommunications and information theory
• ISSN: 1051-8215; 1558-2205
• DOI: 10.1109/TCSVT.2011.2163980

Moments extraction from high resolution images in real time may require a large amount of hardware resources. Using a direct method may involve a critically high operating frequency. This paper presents two improved digital-filter based moment accelerators, as exemplified by a Tchebichef moments computation engine, to introduce features that contribute to an area-efficient and timing-efficient accelerator design. The design of the accelerators invariably consists of two on-chip units: the digital filter and the matrix multiplication units. Among the features introduced are: a data-shifting means, a filter load distribution method, a reduced set of column filters, sectioned left shifters, a double-line buffer, time-multiplexed and pipelined matrix multiplication sections, and multichip amenable features. A total of 98 frames of test data from high definition videos, real and synthetic images are used in the functional tests. The single-chip field-programmable gate array implementation results show the successful realizations of accelerators capable of moment computations of (31, 31) orders, at 50 frames of 1920 × 1080 8-bit pixels per second, and (63, 63) orders, at 30 frames of 512 × 512 pixels per second. These performances have exceeded that of existing multichip and multiplatform designs.