Reducing the Multiplier-Complexity of Massively Parallel Polyphase 2D IIR Broadband Beam Filters

• Published in: Circuits, systems, and signal processing systems, and signal processing, 2012-06, Vol.31 (3), p.1229-1243
• Main Authors: Madanayake, Arjuna, Gunaratne, Thushara K., Bruton, Leonard T.
• Format: Article
• Language: English
• Subjects: Architecture; Beams (structural); Broadband; Circuits; Circuits and Systems; Complexity; Electrical Engineering; Electrical equipment; Electronics and Microelectronics; Engineering; Instrumentation; INT; Short Paper; Signal flow graphs; Signal processing; Signal,Image and Speech Processing; Two dimensional
• ISSN: 0278-081X; 1531-5878
• DOI: 10.1007/s00034-011-9370-1

The superior broadband performance of 2D IIR frequency-planar beam filters, relative to conventional 2D FIR true-time-delay beamforming, has recently been reported using computational electromagnetics and real-time emulations on an antenna test range, resulting in significant improvements of bit-error-rates (BERs) in the presence of broadband interference. Further, massively parallel systolic VLSI circuit polyphase architectures have also been reported (Madanayake et al. in Int. J. Circuit Theory Appl. 2010 ) for the case of the direct-form signal flow graph (SFG) architecture, operating at a maximum throughput of M-(antenna)-frames-per-clock-cycle (MFPCC). The superior broadband performance of 2D IIR frequency-planar beam filters is extended here from the direct-form signal flow graph (SFG) architecture (Madanayake et al. in Int. J. Circuit Theory Appl. 2010 ) to the novel differential-form SFG architecture in order to reduce overall complexity. The proposed method employs a differential-form polyphase 2D IIR frequency-planar beam SFG, and a corresponding circuit architecture, to implement the required input-output 2D space-time difference equation. The resultant digital hardware has the significant advantage of much-reduced multiplier complexity, relative to the direct-form structure. For example, when look-ahead pipelining is not employed and for polyphase architectures having two, three, and four phases, the corresponding reductions in multiplier complexity are 20%, 28.6% and 33.3%, respectively. A proof-of-concept prototype circuit is designed and implemented on a Xilinx Sx35 FPGA device for the two-phase case, operating at a frame-rate of 132 million linear frames per second on the uniform linear array (ULA), corresponding to 2-frames-per-clock-cycle at a circuit clock frequency of 66 MHz. The circuit is optimized for low critical path delays (CPDs) using look-ahead pipelining of order three. For ultra-wideband (UWB) radio-frequency (RF) implementations, in such fields as radio astronomy, radar and wireless communications, custom VLSI versions of the proposed circuits are required.