A dividing ratio changeable digital PLL with low jitter using a multiphase clock divider

• Published in: Electronics and communications in Japan 2011-11, Vol.94 (11), p.55-62
• Main Authors: Fujimoto, Kuniaki, Yahara, Mitsutoshi, Sasaki, Hirofumi
• Format: Article
• Language: English
• Subjects: Circuits; Clocks; Digital; Dividers; Jitter; Multiphase; multiphase clock; On-line systems; PLL; pull-in range; Steady state
• ISSN: 1942-9533; 1942-9541; 1942-9541
• DOI: 10.1002/ecj.10340

Since phase‐locked loops (PLL) are used in the clock extraction of digital communications and high‐density digital recording, it is required to have simultaneously low jitter, fast pull‐in, and wide lock‐in range characteristics. However, in the case of the conventional dividing ratio changeable digital PLL based on phase state memory and double clock‐edge detection (PM‐DCPLL), the output jitter in the steady state becomes no less than half the pulse width of the base clock controlling the loop, and the upper bound frequency of the lock‐in range is limited accordingly. In this paper, we propose a dividing ratio changeable digital phase‐locked loop (MC‐DCPLL) with low jitter, wide lock‐in range, and fast pull‐in characteristics using a multiphase clock divider. Since the output jitter of this circuit is one phase difference of the multiphase clock in steady state, the circuit can reduce the output jitter to 1/k of that of a conventional PM‐DCPLL when a k phase clock is used. Therefore, the upper bound frequency becomes k times that of a conventional PM‐DCPLL. Furthermore, the initial pull‐in is completed in one period of the input signal by using the initial pull‐in circuit. © 2011 Wiley Periodicals, Inc. Electron Comm Jpn, 94(11): 55–62, 2011; Published online in Wiley Online Library (wileyonlinelibrary.com). DOI 10.1002/ecj.10340