Static noise margin enhancement by flex-pass-gate SRAM

• Published in: Electronics and communications in Japan 2011-08, Vol.94 (8), p.57-64
• Main Authors: O'uchi, Shin-Ichi, Masahara, Meishoku, Sakamoto, Kunihiro, Endo, Kazuhiko, Liu, Yungxun, Matsukawa, Takashi, Sekigawa, Toshihiro, Koike, Hanpei, Suzuki, Eiichi
• Format: Article
• Language: English
• Subjects: asymmetric oxide four-terminal FinFET; Asymmetry; Computer simulation; FinFET; four-terminal FinFET; Gates; Monte Carlo methods; Noise; On-line systems; pass gate; SRAM; static noise margin; Static random access memory; Strategy
• ISSN: 1942-9533; 1942-9541; 1942-9541
• DOI: 10.1002/ecj.10217

A flex‐pass‐gate SRAM, that is, a fin‐type field effect transistor‐based (FinFET‐based) SRAM, is proposed to enhance the noise margin during both read and write operations. In its cell, the flip‐flop is composed of the usual three‐terminal (3T) FinFETs and the pass gates are composed of four‐terminal (4T) FinFETs. The 4T‐FinFETs enable the adoption of dynamic threshold‐voltage (Vt) control in the pass gates. During a write operation, the Vt of the pass gates is lowered to enhance the writing speed and stability. During the read operation, on the other hand, the Vt is raised to enhance the static noise margin. An asymmetric‐oxide 4T‐FinFET is helpful in managing the leakage current through the pass gate. In this paper, a design strategy for the pass gate with an asymmetric gate oxide is considered, and a TCAD‐based Monte Carlo simulation reveals that the flex‐pass‐gate SRAM based on that design strategy may be expected to be effective in the half‐pitch 32‐nm technology for low standby power (LSTP) applications, even taking into account the variability in device performance. © 2011 Wiley Periodicals, Inc. Electron Comm Jpn, 94(8): 57–64, 2011; Published online in Wiley Online Library (wileyonlinelibrary.com). DOI 10.1002/ecj.10217