SEU resistance in advanced SOI-SRAMs fabricated by commercial technology using a rad-hard circuit design

We fabricate 128 Kbit SRAMs using a rad-hard circuit design based on a mixed-mode three-dimensional simulation in a commercial silicon-on-insulator foundry with 0.2 /spl mu/m design rules. Appropriate design increases the critical linear energy transfer of single-event upset over 164.4 MeV/(mg/cm/su...

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Bibliographic Details
Published in:IEEE transactions on nuclear science 2002-12, Vol.49 (6), p.2965-2968
Main Authors: Hirose, K., Saito, H., Kuroda, Y., Ishii, S., Fukuoka, Y., Takahashi, D.
Format: Article
Language:English
Subjects:
Circuit design
Circuit simulation
Circuit synthesis
Energy exchange
Energy transfer
Foundries
Immune system
MOSFETs
Radiation hardening
Silicon on insulator technology
Simulation
Single event upset
Space technology
Substrates
Three dimensional
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Summary:We fabricate 128 Kbit SRAMs using a rad-hard circuit design based on a mixed-mode three-dimensional simulation in a commercial silicon-on-insulator foundry with 0.2 /spl mu/m design rules. Appropriate design increases the critical linear energy transfer of single-event upset over 164.4 MeV/(mg/cm/sup 2/).
ISSN:0018-9499
1558-1578
DOI:10.1109/TNS.2002.805978