Static-switching pulse domino: A switching-aware design technique for wide fan-in dynamic multiplexers

In wide fan-in dynamic multiplexers, the two phase evaluate-precharge operation leads to high switching activity at the dynamic and the output nodes introducing a significant power penalty. To address this issue, the switching-aware design techniques are being explored but these existing techniques...

Full description

Saved in:
Bibliographic Details
Published in:Integration (Amsterdam) 2012-06, Vol.45 (3), p.253-262
Main Authors: Singh, Rahul, Hong, Gi-Moon, Kim, Mino, Park, Jihwan, Shin, Woo-Yeol, Kim, Suhwan
Format: Article
Language:English
Subjects:
Applied sciences
Circuit properties
CMOS
Design. Technologies. Operation analysis. Testing
Domino logic
Dynamic circuits
Dynamic tests
Dynamics
Electric, optical and optoelectronic circuits
Electronic circuits
Electronics
Exact sciences and technology
Gates
High speed
Integrated circuits
Integrated circuits by function (including memories and processors)
Low-power design
Multiplexers
Noise immunity
Oscillators, resonators, synthetizers
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Simulation
Switching
Switching activity
Switching, multiplexing, switched capacity circuits
Terminals
Citations: Items that this one cites
Items that cite this one
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:In wide fan-in dynamic multiplexers, the two phase evaluate-precharge operation leads to high switching activity at the dynamic and the output nodes introducing a significant power penalty. To address this issue, the switching-aware design techniques are being explored but these existing techniques suffer from design inflexibilities. In this paper, we propose a pulse domino switching-aware technique, called SSPD, to reduce the overall power consumption of a wide fan-in dynamic gate by having static-like switching behavior at the dynamic node, and the gate input/output terminals. A conditional pulse generator is also proposed, which enables the SSPD multiplexers to be easily adapted to a wide set of noise and delay specifications. Simulation results of 8-bit and 16-bit dynamic multiplexers designed and simulated in a 1.2-V 90-nm CMOS process show that the SSPD technique can reduce the average power by up to 21% and 36%, respectively, when compared to the conventional footless domino technique.
ISSN:0167-9260
1872-7522
DOI:10.1016/j.vlsi.2011.11.013