A novel method to improve cell endurance window in source-side injection split gate flash memory

• Published in: Microelectronics and reliability 2012-06, Vol.52 (6), p.1055-1059
• Main Authors: Tsair, Yong-Shiuan, Fang, Yean-Kuen, Juang, Feng-Renn, Wang, Yu-Hsiung, Chu, Wen-Ting, Lin, Yung-Tao, Tran, Luan
• Format: Article
• Language: English
• Subjects: Acceptability; Applied sciences; Design. Technologies. Operation analysis. Testing; Durability; Electronics; Endurance; Exact sciences and technology; Flash memory (computers); Gates; Integrated circuits; Integrated circuits by function (including memories and processors); Programming; Ramps; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Statistics
• ISSN: 0026-2714; 1872-941X
• DOI: 10.1016/j.microrel.2011.12.016

To enhance cell endurance window of a split gate flash memory, we used a ramp pulse with long rising time to replace the conventional square pulse for programming. The change is based on the study of the electric field at electron injection point (EG) related to programming time. Statistic measurements on various samples including different technologies, cell locations (even or odd) and rise times were done. The results confirm that the read currents shift under erase state (ΔIr1) could be improved significantly with an acceptable programming speed by the proposed method. For example, as increasing the rising time from 0.1μs to 20μs for the conventional square pulse and the ramp pulse respectively, after 1M cycling the ΔIr1 is reduced from 64.8% to 36.2% with an acceptable minimum programming time of 12.5μs.