HIGH SPEED CONTINUOUS-TIME BANDPAS capital sigma Delta ADC FOR MIXED SIGNAL VLSI

With the unremitting progress in VLSI technology, there is a commensurate increase in performance demand on analog to digital converter and are now being applied to wideband communication systems. sigma Delta ( capital sigma Delta ) converter is a popular technique for obtaining high resolution with...

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Bibliographic Details
Published in:International journal of VLSI design & communication systems 2012-04, Vol.3 (2), p.63-63
Main Authors: HarshaVardhini, P A, MadhaviLatha, M
Format: Article
Language:English
Subjects:
Deltas
Design engineering
High speed
Integrated circuits
Modulators
Power consumption
Sampling
Very large scale integration
Online Access:Get full text
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Summary:With the unremitting progress in VLSI technology, there is a commensurate increase in performance demand on analog to digital converter and are now being applied to wideband communication systems. sigma Delta ( capital sigma Delta ) converter is a popular technique for obtaining high resolution with relatively small bandwidth. capital sigma Delta ADCs which trade sampling speed for resolution can benefit from the speed advantages of nm-CMOS technologies. This paper compares various Band pass sigma Delta ADC architectures, both continuous-time and discrete-time, in respect of power consumption and SNDR. Design of 2nd order multibit continuous time band pass capital sigma Delta modulator is discussed with the methods to resolve DAC non-idealities.
ISSN:0976-1527
0976-1357