Area-time efficient multi-modulus adders and their applications

Multi-modulus architectures, that is, architectures that can deal with more than one modulo cases, are very useful for reconfigurable processors and fault-tolerant systems that are based on the residue number system (RNS). Two novel architectures are proposed for multi-modulus adders that support th...

Full description

Saved in:
Bibliographic Details
Published in:Microprocessors and microsystems 2012-07, Vol.36 (5), p.409-419
Main Authors: Vergos, H.T., Bakalis, D.
Format: Article
Language:English
Subjects:
Architecture
Channels
Delay
Fault tolerance
Microprocessors
Modulo 2n ± 1 arithmetic
Multi-modulus architectures
Parallel prefix carry computation
Power dissipation
Processors
Residue number system
Residue number systems
Citations: Items that this one cites
Items that cite this one
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:Multi-modulus architectures, that is, architectures that can deal with more than one modulo cases, are very useful for reconfigurable processors and fault-tolerant systems that are based on the residue number system (RNS). Two novel architectures are proposed for multi-modulus adders that support the most common moduli cases in RNS channels, that is, modulo 2n−1, 2n and 2n+1. The proposed architectures use parallel prefix carry computation units composed of log2n levels. The experimental results show that the resulting adders are significantly faster and/or smaller than the earlier proposals. Multi-modulus subtractors, multipliers and squarers that rely on the use of the proposed multi-modulus adders are also presented. The last two are shown experimentally to outperform the currently most efficient ones in area, delay and dynamic power dissipation terms.
ISSN:0141-9331
1872-9436
DOI:10.1016/j.micpro.2012.02.004