A networks-on-chip architecture design space exploration – The LIB

• Published in: Computers & electrical engineering 2009-11, Vol.35 (6), p.817-836
• Main Authors: Liu, Peng, Xia, Bingjie, Xiang, Chunchang, Wang, Xiaohang, Wang, Weidong, Yao, Qingdong
• Format: Article
• Language: English
• Subjects: Architecture; Blocking; Construction; Design engineering; Interconnection; IP cores; Mathematical models; Multi-processor systems-on-chip; Networks; Networks-on-chip; Protocols; Space exploration
• ISSN: 0045-7906; 1879-0755
• DOI: 10.1016/j.compeleceng.2008.11.027

Many on-chip network circuit and architecture techniques are incompatible with modern design flows, making them unsuitable for use in systems-on-chip. This paper presents a networks-on-chip (NoC) architecture design space exploration method for multi-processor systems-on-chip architecture. The NoC architecture design space is designed with a Layer-Interactive-Building block (LIB) methodology that is divided into three layers: application layer, link/network layer, and physical layer. The suggested LIB design paradigmatic philosophy provides modular building block structure in both hardware and software and the protocols for their interconnection in the three architecture layers. Using LIB the designer can easily select these building blocks to build application-specific NoCs to meet different application requirements such as media, graphic, software radio and communication network applications. The LIB provides the NoC building blocks, architecture interacting systems-on-chip components, the programming models and application mapping strategies. The LIB can be used as a complementary library and tools for future on-chip interconnection network design.