Distributed clock gating for power reduction of a programmable waveform generator for neural stimulation

• Published in: 2012 Annual International Conference of the IEEE Engineering in Medicine and Biology Society 2012-01, Vol.2012, p.3878-3881
• Main Authors: Noorsal, E., Sooksood, K., Bihr, U., Becker, J., Ortmanns, M.
• Format: Article
• Language: English
• Subjects: Clocks; Electrodes; Logic gates; Power demand; Registers; Shape; Timing
• ISSN: 1094-687X; 1558-4615; 2694-0604
• DOI: 10.1109/EMBC.2012.6346814

This paper describes how to employ distributed clock gating to achieve an overall low power design of a programmable waveform generator intended for a neural stimulator. The power efficiency is enabled using global timing control combined with local amplitude distribution over a bus to the local stimulator frontends. This allows the combination of local and global clock gating for complete sub-blocks of the design. A counter and a shifter employed at the local digital stimulator reduce the design complexity for the waveform generation and thus the overall power consumptions. The average power results indicate that 63% power can be saved for the global stimulator control unit and 89-96% power can be saved for the local digital stimulator by using the proposed approach. The circuit has been implemented and successfully tested in a 0.35 μm AMS HVCMOS technology.