An Efficient 4-D 8PSK TCM Decoder Architecture

This paper presents an efficient architecture for a 4-D eight-phase-shift-keying trellis-coded-modulation (TCM) decoder. First, a low-complexity architecture for the transition metric unit is proposed based on substructure sharing. This scheme significantly reduces the required computation without d...

Full description

Saved in:
Bibliographic Details
Published in:IEEE transactions on very large scale integration (VLSI) systems 2010-05, Vol.18 (5), p.808-817
Main Authors: He, Jinjin, Wang, Zhongfeng, Liu, Huping
Format: Article
Language:English
Subjects:
Add-compare-select unit (ACSU)
Algorithms
Applied sciences
Architecture
Circuit properties
Clocks
Computation
Computer architecture
Convolutional codes
Decoders
Degradation
Design. Technologies. Operation analysis. Testing
Digital modulation
Electric, optical and optoelectronic circuits
Electronic circuits
Electronics
Encoders
Exact sciences and technology
Integrated circuits
Iterative decoding
Modulation coding
Multidimensional systems
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Signal convertors
Studies
Substructures
T -algorithm
trellis-coded modulation (TCM)
Very large scale integration
Viterbi algorithm
Viterbi decoder (VD)
Viterbi decoders
VLSI
Citations: Items that this one cites
Items that cite this one
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:This paper presents an efficient architecture for a 4-D eight-phase-shift-keying trellis-coded-modulation (TCM) decoder. First, a low-complexity architecture for the transition metric unit is proposed based on substructure sharing. This scheme significantly reduces the required computation without degrading the performance. Then, a new hybrid T -algorithm for a Viterbi decoder is developed by applying a T -algorithm on both branch metrics (BMs) and path metrics (PMs). TCM encoders usually employ high-rate convolutional codes that yield many more transition paths per state than low-rate codes do. This makes it feasible to purge unnecessary additions by applying the T -algorithm on BMs. Applying the T -algorithm on BMs instead of PMs allows one to move the ¿search-for-the-optimal¿ operation out of the add-compare-select-unit (ACSU) loop. Hence, the clock speed will not be affected. In addition, by combining the T -algorithm on BMs and the T -algorithm on PMs, the hybrid T -algorithm can reduce the computations required with the conventional T -algorithm on PMs by as much as 50%.
ISSN:1063-8210
1557-9999
DOI:10.1109/TVLSI.2009.2015325