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A Low THD, Low Power, High Output-Swing Time-Mode-Based Tunable Oscillator Via Digital Harmonic-Cancellation Technique
An architectural solution for designing and implementing low THD oscillators is presented. A digital harmonic-cancellation-block is used to suppress the low-frequency harmonics while a passive, inherently linear, filter is used to suppress the high-frequency ones. The proposed technique eliminates t...
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Published in: | IEEE journal of solid-state circuits 2010-05, Vol.45 (5), p.1061-1071 |
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Main Authors: | , |
Format: | Article |
Language: | English |
Subjects: | |
Citations: | Items that this one cites Items that cite this one |
Online Access: | Get full text |
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Summary: | An architectural solution for designing and implementing low THD oscillators is presented. A digital harmonic-cancellation-block is used to suppress the low-frequency harmonics while a passive, inherently linear, filter is used to suppress the high-frequency ones. The proposed technique eliminates the need for typical high-Q BPF to suppress the harmonics. Thus, eradicates the effect of increasing device nonlinearities in the nanometric technologies by having pure digital solution. In addition, eliminating the need for high-Q band-pass-filter (BPF) releases the output swing from the constraints imposed by the linearity of the filter. The prototype is fabricated in 0.13 ¿m CMOS technology. Measurement results show -72 dB THD at 10 MHz along with a differential output swing of 228 mV pp . The oscillator prototype can be tuned from 5 MHz to 11 MHz with less than 4.5 dB variations in the THD. The circuit consumes 3.37 mA from 1.2 V supply at 10 MHz and occupies an area of 0.186 mm 2 . As the performance depends solely on the timing precision of digital signals, the proposed oscillator is considered the best time-mode-based oscillator in literature. |
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ISSN: | 0018-9200 1558-173X |
DOI: | 10.1109/JSSC.2010.2043885 |