SleepWalker: A 25-MHz 0.4-V Sub- hbox mm 2 7- mu hbox W / MHz Microcontroller in 65-nm LP/GP CMOS for Low-Carbon Wireless Sensor Nodes

Integrated circuits for wireless sensor nodes (WSNs) targeting the Internet-of-Things (IoT) paradigm require ultralow-power consumption for energy-harvesting operation and low die area for low-cost nodes. As the IoT calls for the deployment of trillions of WSNs, minimizing the carbon footprint for W...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 2013-01, Vol.48 (1), p.20-32
Main Authors: Bol, David, De Vos, Julien, Hocquet, Cedric, Botman, Francois, Durvaux, Francois, Boyd, Sarah, Flandre, Denis, Legat, Jean-Didier
Format: Article
Language:English
Subjects:
Carbon
Chips
Clocks
Converters
Direct current
Environmental impact
Microcontrollers
Sensors
Online Access:Get full text
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Summary:Integrated circuits for wireless sensor nodes (WSNs) targeting the Internet-of-Things (IoT) paradigm require ultralow-power consumption for energy-harvesting operation and low die area for low-cost nodes. As the IoT calls for the deployment of trillions of WSNs, minimizing the carbon footprint for WSN chip manufacturing further emerges as a third target in a design-for-the-environment (DfE) perspective. The SleepWalker microcontroller is a 65-nm ultralow-voltage SoC based on the MSP430 architecture capable of delivering increased speed performances at 25 MHz for only 7 mu hbox W / MHz at 0.4 V. Its hbox sub - mm 2 die area with low external component requirement ensures a low carbon footprint for chip manufacturing. SleepWalker incorporates an on-chip adaptive voltage scaling (AVS) system with DC/DC converter, clock generator, memories, sensor and communication interfaces, making it suited for WSN applications. An LP/GP process mix is fully exploited for minimizing the energy per cycle, with power gating to keep stand-by power at 1.7 mu hbox W . By incorporating a glitch-masking instruction cache, system power can be reduced by up to 52%. The AVS system ensures proper 25-MHz operation over process and temperature variations from - 40 [compfn] C to + hbox 85 [compfn] hbox C , with a peak efficiency of the DC/DC converter above 80%. Finally, a multi- V t clock tree reduces variability-induced clock skew by 3 to ensure robust timing closure down to 0.3 V.
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2012.2218067