An Efficient Multimode Multiplier Supporting AES and Fundamental Operations of Public-Key Cryptosystems

• Published in: IEEE transactions on very large scale integration (VLSI) systems 2010-04, Vol.18 (4), p.553-563
• Main Authors: Wang, Chen-Hsing, Chuang, Chieh-Lin, Wu, Cheng-Wen
• Format: Article
• Language: English
• Subjects: Advanced Encryption Standard (AES); Algorithm design and analysis; Algorithms; and Adleman (RSA); Asymmetry; Clocks; Communication system security; composite field arithmetic; Costs; Data security; digital signal algorithm (DSA); Elliptic curve cryptography; Elliptic-curve cryptography (ECC); Hardware; Keys; Montgomery multiplication (MM); Multiplication; Multipliers; Pipelines; Polynomials; Public key cryptography; Rivest; Shamir; Throughput; Very large scale integration
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2009.2013958

This paper presents a highly efficient multimode multiplier supporting prime field, namely, polynomial field, and matrix-vector multiplications based on an asymmetric word-based Montgomery multiplication (MM) algorithm. The proposed multimode 128 × 32 b multiplier provides throughput rates of 441 and 511 Mb/s for 256-b operands over GF(P) and GF(2 n ) at a clock rate of 100 MHz, respectively. With 21 930 additional gates for Advanced Encryption Standard (AES), the multiplier is extended to provide 1.28-, 1.06-, and 0.91-Gb/s throughput rates for 128-, 192-, and 256-b keys, respectively. The comparison result shows that the proposed integration architecture outperforms others in terms of performance and efficiency for both AES and MM that is essential in most public-key cryptosystems.