FPGA Implementation of Deblocking Filter Custom Instruction Hardware on NIOS - II Based SOC

This paper presents a frame work for hardware acceleration for post video processing system implemented on FPGA. The deblocking filter algorithms ported on SOC having Altera NIOS-II soft core processor.SOC designed with the help of SOPC builder .Custom instructions are chosen by identifying the most...

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Bibliographic Details
Published in:International journal of VLSI design & communication systems 2011-12, Vol.2 (4), p.27-35
Main Authors: Naresh, Bolla Leela, Narayana Rao, Ramesh, Addanki Purna
Format: Article
Language:English
Subjects:
Algorithms
Communication systems
Construction
Design engineering
Field programmable gate arrays
Hardware
Microprocessors
Tasks
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Summary:This paper presents a frame work for hardware acceleration for post video processing system implemented on FPGA. The deblocking filter algorithms ported on SOC having Altera NIOS-II soft core processor.SOC designed with the help of SOPC builder .Custom instructions are chosen by identifying the most frequently used tasks in the algorithm and the instruction set of NIOS-II processor has been extended. Deblocking filter new instruction added to the processor that are implemented in hardware and interfaced to the NIOSII processor. New instruction added to the processor to boost the performance of the deblocking filter algorithm. Use of custom instructions the implemented tasks have been accelerated by 5.88%. The benefit of the speed is obtained at the cost of very small hardware resources.
ISSN:0976-1357
0976-1527
0976-1357
DOI:10.5121/vlsic.2011.2403