A Digitally Modulated Polar CMOS Power Amplifier With a 20-MHz Channel Bandwidth

This paper presents a CMOS RF power amplifier that employs a digital polar architecture to improve the overall power efficiency when amplifying signals with high linearity requirements. The power amplifier comprises 64 parallel RF amplifiers that are driven by a constant envelope RF phase-modulated...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 2008-10, Vol.43 (10), p.2251-2258
Main Authors: Kavousian, A., Su, D.K., Hekmat, M., Shirvani, A., Wooley, B.A.
Format: Article
Language:English
Subjects:
Amplifiers
Applied sciences
Bandwidth
Channels
Circuit properties
CMOS
CMOS RF
CMOS technology
Design. Technologies. Operation analysis. Testing
Digital modulation
Electric, optical and optoelectronic circuits
Electrical engineering. Electrical power engineering
Electronic circuits
Electronic equipment and fabrication. Passive components, printed wiring boards, connectics
Electronics
Envelopes
Exact sciences and technology
High power amplifiers
IEEE 802.11g
Image converters
Integrated circuits
L-fold linear interpolation
Linearity
polar transmitter
power amplifier
Power amplifiers
Power electronics, power supplies
Radio frequencies
Radio frequency
Radiofrequency amplifiers
RF signals
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
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Summary:This paper presents a CMOS RF power amplifier that employs a digital polar architecture to improve the overall power efficiency when amplifying signals with high linearity requirements. The power amplifier comprises 64 parallel RF amplifiers that are driven by a constant envelope RF phase-modulated signal. The unit amplifiers are digitally activated by a 6-bit envelope code to construct a non-constant envelope RF output, thereby performing a digital-to-RF conversion. In order to suppress the spectral images resulting from the discrete-time to continuous-time conversion of the envelope, the use of oversampling and four-fold linear interpolation is explored. An experimental prototype of the polar amplifier has been integrated in a 0.18- mum CMOS technology, occupies a total die area of 1.8 mm 2 , operates at a 1.6-GHz carrier frequency with a channel bandwidth of 20 MHz. For an OFDM signal, it achieves a power-added efficiency of 6.7% with an EVM of - 26.8 dB while delivering 13.6 dBm of linear output power and drawing 145 mA from a 1.7-V supply.
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2008.2004338