Modified Booth Multiplier using Wallace Structure and Efficient Carry Select Adder

The multiplier forms the core of systems such as FIR filters, Digital Signal Processors and Microprocessors etc. This paper presents a model of two different 16X16 bit multipliers. First is Radix-4 Multiplier with SQRT CSLA and Second one is Radix -4 multiplier with Modified SQRT CSLA. Modified Boot...

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Bibliographic Details
Published in:International journal of computer applications 2013-01, Vol.68 (13), p.39-42
Main Authors: Sharma, Neeta, Sindal, Ravi
Format: Article
Language:English
Subjects:
Algorithms
Blocking
Computer simulation
Delay
Microprocessors
Multipliers
Processors
VHDL
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Summary:The multiplier forms the core of systems such as FIR filters, Digital Signal Processors and Microprocessors etc. This paper presents a model of two different 16X16 bit multipliers. First is Radix-4 Multiplier with SQRT CSLA and Second one is Radix -4 multiplier with Modified SQRT CSLA. Modified Booth Algorithm is used for Partial Products Generation. Wallace Tree Structure is used to accumulate partial Products. SQRT Carry Select Adder is used for addition of last two rows. SQRT Carry Select Adder uses non uniform block size & Modified SQRT Carry Select Adder uses non-uniform block size with Binary to excess one Converter . Both the adders proved to be fast as compared to regular carry select adder. An efficient VHDL code has been written & successfully synthesized & Simulated using Xilinx ISE 12. 1. Simulation results shows that the delay of both the multipliers is reduced & the number of logic levels is also reduced with slight increase in number of slices & LUTS as compared to multiplier that uses regular carry select adder.
ISSN:0975-8887
0975-8887
DOI:10.5120/11643-7130