An efficient threshold voltage generation for SAR ADCs

In this paper, a new architecture for successive-approximation register (SAR) analog-to-digital converters (ADCs) is presented. In the proposed scheme, the threshold voltage for each comparison is divided into two parts. This results in appreciably less switching energy and less total capacitance wi...

Full description

Saved in:
Bibliographic Details
Published in:Analog integrated circuits and signal processing 2013-04, Vol.75 (1), p.161-169
Main Authors: Khoshakhlagh, Mohammad, Yavari, Mohammad
Format: Article
Language:English
Subjects:
Capacitance
Circuits
Circuits and Systems
Electrical Engineering
Engineering
Mathematical analysis
Mixed Signal Letter
Registers
Signal,Image and Speech Processing
Simulation
Switching
Synthetic aperture radar
Threshold voltage
Citations: Items that this one cites
Items that cite this one
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:In this paper, a new architecture for successive-approximation register (SAR) analog-to-digital converters (ADCs) is presented. In the proposed scheme, the threshold voltage for each comparison is divided into two parts. This results in appreciably less switching energy and less total capacitance without a substantial increase in digital complexity compared to the conventional SAR ADC. Analytical calculations and circuit level simulation results in the context of a 10-bit 100 kS/s ADC are provided to verify the usefulness of the proposed SAR ADC scheme revealing 87 % less switching power and 40 % less total capacitance in comparison with the conventional SAR ADC.
ISSN:0925-1030
1573-1979
DOI:10.1007/s10470-013-0028-8