Avalanche behavior of power MOSFETs under different temperature conditions

The ability of high-voltage power MOSFETs to withstand avalanche events under different temperature conditions are studied by experiment and two-dimensional device simulation. The experiment is performed to investigate dynamic avalanche failure behavior of the domestic power MOSFETs which can occur...

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Bibliographic Details
Published in:Journal of semiconductors 2011, Vol.32 (1), p.27-32
Main Author: 陆江 王立新 卢烁今 王雪生 韩郑生
Format: Article
Language:English
Subjects:
Avalanches
Computer simulation
Devices
Domestic
Failure mechanisms
MOSFETs
Semiconductors
Two dimensional
功率MOSFET
器件模拟
寄生双极晶体管
工作温度范围
温度条件
研究试验
行为
雪崩
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Summary:The ability of high-voltage power MOSFETs to withstand avalanche events under different temperature conditions are studied by experiment and two-dimensional device simulation. The experiment is performed to investigate dynamic avalanche failure behavior of the domestic power MOSFETs which can occur at the rated maximum operation temperature range （-55 to 150 ℃）. An advanced ISE TCAD two-dimensional mixed mode simulator with thermodynamic non-isothermal model is used to analyze the avalanche failure mechanism. The unclamped inductive switching measurement and simulation results show that the parasitic components and thermal effect inside the device will lead to the deterioration of the avalanche reliability of power MOSFETs with increasing temperature. The main failure mechanism is related to the parasitic bipolar transistor activity during the occurrence of the avalanche behavior.
ISSN:1674-4926
DOI:10.1088/1674-4926/32/1/014001