An I/Q DAC with gain matching circuit for a wireless transmitter

This paper presents a two-channel 12-bit current-steering digital-to-analog converter (DAC) for I and Q signal paths in a wireless transmitter. The proposed DAC has a full-scale output current with an adjusting range of 2 to 10 mA. A gain matching circuit is proposed to reduce gain mismatch between...

Full description

Saved in:
Bibliographic Details
Published in:Journal of semiconductors 2013-06, Vol.34 (6), p.65006-1-6
Main Authors: Tang, Hualian, Zhuang, Yiqi, Jing, Xin, Zhang, Li
Format: Article
Language:English
Subjects:
Channels
Circuits
Gain
Matching
Noise levels
Semiconductors
Transmitters
Tuning
Citations: Items that this one cites
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:This paper presents a two-channel 12-bit current-steering digital-to-analog converter (DAC) for I and Q signal paths in a wireless transmitter. The proposed DAC has a full-scale output current with an adjusting range of 2 to 10 mA. A gain matching circuit is proposed to reduce gain mismatch between the I and Q channels. The tuning range is plus or minus 24% of full scale and the minimum resolution is 1/16 LSB. To further improve its dynamic performance, the switch driver and current cell are optimized to minimize glitch energy. The chip has been processed in a standard 0.13 mu m CMOS technology. Gain mismatch between a I-channel DAC and a Q-channel DAC is measured to be approximately 0.13%. At 120-MSPS sample rate for 1 MHz sinusoidal signal, the spurious free dynamic range (SFDR) is 75 dB. The total power dissipation is 62 mW and has an active area of 1.08 mm super(2).
ISSN:1674-4926
DOI:10.1088/1674-4926/34/6/065006