Systematic Design Methodology of a Wideband Multibit Continuous-Time Delta-Sigma Modulator

Systematic design of a low power, wideband and multi-bit continuous-time delta-sigma modulator (CTDSM) is presented. The design methodology is illustrated with a 640 MS/s, 20 MHz signal bandwidth 4th order 2-bit CTDMS implemented in 0.18 µm CMOS technology. The implemented design achieves a peak SND...

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Bibliographic Details
Published in:International journal of microwave science and technology 2013, Vol.2013 (2013), p.1-5
Main Authors: Anand, Awinash, Koirala, Nischal, Pokharel, Ramesh K., Kanaya, Haruichi, Yoshida, Keiji
Format: Article
Language:English
Subjects:
CMOS
Compensation
Design engineering
Education
Methodology
Microwaves
Modulators
Noise
Noise levels
Spectrum allocation
Wideband
Wireless communications
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Summary:Systematic design of a low power, wideband and multi-bit continuous-time delta-sigma modulator (CTDSM) is presented. The design methodology is illustrated with a 640 MS/s, 20 MHz signal bandwidth 4th order 2-bit CTDMS implemented in 0.18 µm CMOS technology. The implemented design achieves a peak SNDR of 65.7 dB and a high dynamic range of 70 dB while consuming only 19.7 mW from 1.8 V supply. The design achieves a FoM of 0.31 pJ/conv. Direct path compensation is employed for one clock excess loop delay compensation. In the feedforward topology, capacitive summation using the last opamp eliminates extra summation opamp.
ISSN:1687-5826
1687-5834
DOI:10.1155/2013/275289