Design and Implementation of Complex Floating Point Processor Using FPGA

This article presents complete processor hardware with three arithmetic units. The first arithmetic unit can perform 32-bit integer arithmetic operations. The second unit can perform arithmetic operations such as addition, subtraction, multiplication, division, and square root on 32-bit floating poi...

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Bibliographic Details
Published in:International journal of VLSI design & communication systems 2013-10, Vol.4 (5), p.53-61
Main Authors: Pavuluri, Murali Krishna, T.S.R, Krishna Prasad, ch, Rambabu
Format: Article
Language:English
Subjects:
Arithmetic
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Summary:This article presents complete processor hardware with three arithmetic units. The first arithmetic unit can perform 32-bit integer arithmetic operations. The second unit can perform arithmetic operations such as addition, subtraction, multiplication, division, and square root on 32-bit floating point numbers. The third unit can perform arithmetic operations such as addition, subtraction, multiplication on complex numbers. The proposed architecture avoids that compromise and it is implemented with less number of look-up tables to save around 5500 logic gates. The complex numbers are represented, using a subset of IEEE754 standard floating point format, 16-bits for real part and 16-bits for imaginary part. The floating point arithmetic unit works on 32-bit IEEE754 single precision numbers. The instruction set is specially designed to support integer, floating point and complex floating point arithmetic operations. The on-chip RAM is 8kBytes, and is extendable up to 64kBytes. As the processor is designed to implement on FPGA, the embedded block RAMs are utilized as RAM.
ISSN:0976-1527
0976-1357
DOI:10.5121/vlsic.2013.4504