Novel Mixed Codes for Multiple-Cell Upsets Mitigation in Static RAMs

• Published in: IEEE MICRO 2013-11, Vol.33 (6), p.66-74
• Main Authors: Guo, Jing, Xiao, Liyi, Mao, Zhigang, Zhao, Qiang
• Format: Article
• Language: English
• Subjects: Cache; Circuits; Codes; Complexity theory; Diffusion tensor imaging; doubly transitive invariant code; Encoding; Error correction codes; error-correcting code; Errors; multiple-cell upsets; Random access memory; static RAM; Transient analysis
• ISSN: 0272-1732; 1937-4143
• DOI: 10.1109/MM.2013.125

Error-correcting codes (ECCs) are commonly used to protect static RAM (SRAM) from soft errors induced by particle radiation. The traditional single-error correction, double-error detection (SEC-DED) codes are not enough because transient multiple-cell upsets (MCUs) are becoming major issues in SRAM reliability. One-step majority-logic decodable (OS-MLD) codes that can correct MCUs are a good choice due to low complexity and latency. However, these codes restrict the choice of code-word lengths such that they can't be directly used to protect memories with common word lengths (that is, a power of two). This article proposes novel mixed codes (MCs), which are constructed by doubly transitive invariant (DTI) and Hamming codes, to mitigate MCUs in common memories with lower overheads and higher code rates. For the Hamming codes, the encoder-reuse technique (ERT) is used to minimize area overhead without disturbing the whole encoding and decoding process. In addition, the puncturing technique is used to increase the code rates of the proposed codes. As an application example, the authors evaluate a (64, 42) double-error correction (DEC) MC and compare it with the existing DEC codes. The results show that the proposed MC with higher code rate can not only effectively mitigate MCUs in memories but also reduce the overheads of the extra circuits and memory cells.