Optimized design of Si-cap layer in strained-SiGe channel p-MOSFETs based on computational and experimental approaches

• Published in: Solid-state electronics 2014-01, Vol.91, p.1-8
• Main Authors: Sato-Iwanaga, Junko, Inoue, Akira, Sorada, Haruyuki, Takagi, Takeshi, Rothschild, Aude, Loo, Roger, Biesemans, Serge, Ito, Choshu, Liu, Yang, Dutton, Robert W., Tsuchiya, Hideaki
• Format: Article
• Language: English
• Subjects: Applied sciences; Channels; Device simulation; Electronics; Exact sciences and technology; FET; MOS; Semiconductor; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; SiGe; Transistors
• ISSN: 0038-1101; 1879-2405
• DOI: 10.1016/j.sse.2013.09.010

•Strainde-SiGe channel p-MOSFETs with a Si-cap layer are studied.•The roles of Si-cap layer are clarified by using simulation and experiment.•2D hole distributions is described by considering quantum confinement effect.•Mobility degradation in a SiGe channel by surface scattering is considered.•Insertion of a Si-cap layer is effective to reduce an OFF-state leakage current. In this paper, we study the hole transport properties in strained-SiGe channel p-MOSFETs (sSG pMOSFETs) with a Si-cap layer, which is introduced to avoid degradation of interface quality between gate oxide and channel. By using device simulation considering Ge diffusion, quantum confinement effects, surface roughness scattering and Coulomb scattering due to interface charges, and also experimental measurement, we clarify the roles of a Si-cap layer in sSG pMOSFETs, and furthermore propose its optimized design to obtain a higher device performance. We also demonstrate that the insertion of a Si-cap layer is effective to reduce an OFF-state leakage current owing to an increased band gap energy in the Si-cap layer.