A Native Stochastic Computing Architecture Enabled by Memristors

• Published in: IEEE transactions on nanotechnology 2014-03, Vol.13 (2), p.283-293
• Main Authors: Knag, Phil, Wei Lu, Zhengya Zhang
• Format: Article
• Language: English
• Subjects: CMOS; CMOS integrated circuits; Computation; Density; Devices; Materials; Memory devices; Memristor; Memristors; Probabilistic logic; Programming; Resistance; Resistors; stochastic computing; stochastic number generator; stochastic switching; Stochasticity; Streams; Switches
• ISSN: 1536-125X; 1941-0085
• DOI: 10.1109/TNANO.2014.2300342

A two-terminal memristor device is a promising digital memory for its high integration density, substantially lower energy consumption compared to CMOS, and scalability below 10 nm. However, a nanoscale memristor is an inherently stochastic device, and extra energy and latency are required to make a deterministic memory based on memristors. Instead of enforcing deterministic storage, we take advantage of the nondeterministic memory for native stochastic computing, where the randomness required by stochastic computing is intrinsic to the devices without resorting to expensive stochastic number generation. This native stochastic computing system can be implemented as a hybrid integration of memristor memory and simple CMOS stochastic computing circuits. We use an approach called group write to program memristor memory cells in arrays to generate random bit streams for stochastic computing. Three methods are proposed to program memristors using stochastic bit streams and compensate for the nonlinear memristor write function: voltage predistortion, parallel single-pulse write, and downscaled write and upscaled read. To evaluate these technical approaches, we show by simulation a memristor-based stochastic processor for gradient descent optimization, and k-means clustering. The native stochastic computing based on memristors demonstrates key advantages in energy and speed in compute-intensive, data-intensive, and probabilistic applications.