BTI and HCI first-order aging estimation for early use in standard cell technology mapping

•The aging degradation in the delay of a logic gate is estimated as an aging cost.•All logic delay arcs are considered to provide a more realistic estimative.•The transistor arrangement dependence is explored in the estimated aging cost.•The aging cost has potential use as input to standard cell tec...

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Bibliographic Details
Published in:Microelectronics and reliability 2013-09, Vol.53 (9-11), p.1360-1364
Main Authors: Butzen, P.F., Dal Bem, V., Reis, A.I., Ribas, R.P.
Format: Article
Language:English
Subjects:
Applied sciences
Circuits
CMOS
Design. Technologies. Operation analysis. Testing
Electronics
Exact sciences and technology
Integrated circuits
Interactive
Logic synthesis
Mapping
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Simulation
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Summary:•The aging degradation in the delay of a logic gate is estimated as an aging cost.•All logic delay arcs are considered to provide a more realistic estimative.•The transistor arrangement dependence is explored in the estimated aging cost.•The aging cost has potential use as input to standard cell technology mapping.•The aging cost can also be used to estimate the final circuit degradation. The performance degradation in digital integrated circuit (IC) caused by BTI and HCI aging effects has increased significantly at each new technology node, as well as their importance in terms of circuit reliability throughout the entire circuit lifetime. This work proposes an aging design cost estimation method to be exploited in standard cell IC design flow. This method must be simple and fast, although not so accurate, to be suitable for the intense interactive process during the technology mapping in the logic synthesis phase. The proposed aging cost has been verified and validated through SPICE simulations carried out over a large number of CMOS gates.
ISSN:0026-2714
1872-941X
DOI:10.1016/j.microrel.2013.07.087