A 10 MS/s 8-bit charge-redistribution ADC for hybrid pixel applications in 65 m CMOS

• Published in: Nuclear instruments & methods in physics research. Section A, Accelerators, spectrometers, detectors and associated equipment Accelerators, spectrometers, detectors and associated equipment, 2013-12, Vol.732, p.506-510
• Main Authors: Kishishita, Tetsuichi, Hemperek, Tomasz, Krueger, Hans, Koch, Manuel, Germic, Leonard, Wermes, Norbert
• Format: Article
• Language: English
• Subjects: Arrays; Capacitors; Channels; CMOS; Design engineering; Detectors; Logic; Power consumption
• ISSN: 0168-9002
• DOI: 10.1016/j.nima.2013.05.192

The design and measurement results of an 8-bit SAR ADC, based on a charge-redistribution DAC, are presented. This ADC is characterized by superior power efficiency and small area, realized by employing a lateral metal-metal capacitor array and a dynamic two-stage comparator. To avoid the need for a high-speed clock and its associated power consumption, an asynchronous logic was implemented in a logic control cell. A test chip has been developed in a 65 nm CMOS technology, including eight ADC channels with different layout flavors of the capacitor array, a transimpedance amplifier as a signal input structure, a serializer, and a custom-made LVDS driver for data transmission. The integral (INL) and differential (DNL) nonlinearities are measured below 0.5 LSB and 0.8 LSB, respectively, for the best channel operating at a sampling frequency of 10 MS/s. The area occupies 40 mu m70 mu m for one ADC channel. The power consumption is estimated as 4 mu W at 1 MS/s and 38 mu W at 10 MS/s with a supply rail of 1.2 V. These excellent performance features and the natural radiation hardness of the design, due to the thin gate oxide thickness of transistors, are very interesting for front-end electronics ICs of future hybrid-pixel detector systems.