A zero-crossing based 10-bit 100 MS/s pipeline ADC with controlled current in 90 nm CMOS

In this paper, a new charging technique for low power zero-crossing based circuit pipeline analog-to-digital converters (ADCs) is presented. The charging current sources are implemented as voltage-controlled current sources in order to charge the sampling capacitors based on the error signal. Using...

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Bibliographic Details
Published in:Analog integrated circuits and signal processing 2014-07, Vol.80 (1), p.141-151
Main Authors: Shafti, Ali, Yavari, Mohammad
Format: Article
Language:English
Subjects:
Circuits and Systems
Electrical Engineering
Engineering
Mixed Signal Letter
Signal,Image and Speech Processing
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Summary:In this paper, a new charging technique for low power zero-crossing based circuit pipeline analog-to-digital converters (ADCs) is presented. The charging current sources are implemented as voltage-controlled current sources in order to charge the sampling capacitors based on the error signal. Using this method, the ADC power consumption is reduced while improving the accuracy. The necessary current control block is shared between consecutive stages further reducing the power consumption and die area. The proposed technique is applied to a 10-bit 100 MS/s pipeline ADC designed in a 90 nm CMOS technology with 1 V power supply. Circuit level simulation results using Cadence Spectre show a signal-to-noise and distortion ratio of 55.6 dB with 3.56 mW power consumption resulting in a figure of merit of 72.3 fJ/conv.step without employing any calibration technique.
ISSN:0925-1030
1573-1979
DOI:10.1007/s10470-014-0299-8