Low-Complexity Low-Latency Architecture for Matching of Data Encoded With Hard Systematic Error-Correcting Codes

A new architecture for matching the data protected with an error-correcting code (ECC) is presented in this brief to reduce latency and complexity. Based on the fact that the codeword of an ECC is usually represented in a systematic form consisting of the raw data and the parity information generate...

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Bibliographic Details
Published in:IEEE transactions on very large scale integration (VLSI) systems 2014-07, Vol.22 (7), p.1648-1652
Main Authors: Kong, Byeong Yong, Jo, Jihyuck, Jeong, Hyewon, Hwang, Mina, Cha, Soyoung, Kim, Bongjin, Park, In-Cheol
Format: Article
Language:English
Subjects:
Algorithms
Architecture
Codes
Complexity
Complexity theory
Computational efficiency
Computer architecture
Data comparison
Decoding
Encoding
Error correction
Error correction codes
error-correcting codes (ECCs)
Hamming distance
Matching
Parity
systematic codes
Systematics
tag matching
Very large scale integration
Weight reduction
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Summary:A new architecture for matching the data protected with an error-correcting code (ECC) is presented in this brief to reduce latency and complexity. Based on the fact that the codeword of an ECC is usually represented in a systematic form consisting of the raw data and the parity information generated by encoding, the proposed architecture parallelizes the comparison of the data and that of the parity information. To further reduce the latency and complexity, in addition, a new butterfly-formed weight accumulator (BWA) is proposed for the efficient computation of the Hamming distance. Grounded on the BWA, the proposed architecture examines whether the incoming data matches the stored data if a certain number of erroneous bits are corrected. For a (40, 33) code, the proposed architecture reduces the latency and the hardware complexity by ~32% and 9%, respectively, compared with the most recent implementation.
ISSN:1063-8210
1557-9999
DOI:10.1109/TVLSI.2013.2276076