Analysis of ATPMOS configurations-based 4 × 1 multiplexer with estimation of power and delay

In this article, two consecutive augmenting transistor P-channel metal oxide semiconductor (ATPMOS) configurations are proposed. These two ATPMOS configurations (ST ATPMOS and DT ATPMOS) are implemented on a 4 × 1 (multiplexer) mux circuit. Leakage power dissipation, dynamic power dissipation and de...

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Bibliographic Details
Published in:International journal of electronics 2014-07, Vol.101 (7), p.1006-1018
Main Authors: Jain, Prateek, Akashe, Shyam
Format: Article
Language:English
Subjects:
4 × 1 multiplexer (mux)
Circuits
Delay
dynamic power
dynamic threshold augmenting transistor PMOS (DT ATPMOS)
Dynamics
Leakage
leakage power
Multiplexing
Power dissipation
Power supply
Semiconductor devices
Semiconductors
Simulation
static threshold augmenting transistor PMOS (ST ATPMOS)
Transistors
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Summary:In this article, two consecutive augmenting transistor P-channel metal oxide semiconductor (ATPMOS) configurations are proposed. These two ATPMOS configurations (ST ATPMOS and DT ATPMOS) are implemented on a 4 × 1 (multiplexer) mux circuit. Leakage power dissipation, dynamic power dissipation and delay performance parameters are calculated for both (ST ATPMOS and DT ATPMOS) ATPMOS configurations-based 4 × 1 mux circuits at different values of transistor's width. Due to simulation, it is realised that the leakage power dissipation and dynamic power dissipation are reduced and delay is improved (delay is reduced) in the DT ATPMOS configuration-based mux circuit compared to the ST ATPMOS configuration-based mux circuit. The whole simulation process was carried out in 45-nm technology. The circuits were operated at 1-V power supply.
ISSN:0020-7217
1362-3060
DOI:10.1080/00207217.2013.805391