Exploiting Die-to-Die Thermal Coupling in 3-D IC Placement

In this paper, we propose two methods used in 3-D IC placement that efficiently exploit the die-to-die thermal coupling in the stack. First, through-silicon vias (TSVs) are spread on each die to reduce the local power density and vertically aligned across dies simultaneously to increase thermal cond...

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Bibliographic Details
Published in:IEEE transactions on very large scale integration (VLSI) systems 2014-10, Vol.22 (10), p.2145-2155
Main Authors: Athikulwongse, Krit, Ekpanyapong, Mongkol, Sung Kyu Lim
Format: Article
Language:English
Subjects:
3-D IC
Conductivity
Density
Density measurement
Dies
Force
Heat sinks
Heating
Integrated circuits
Placement
Springs
temperature
Thermal conductivity
Thermal coupling
Three dimensional
Through-silicon vias
through-silicon vias (TSV)
Very large scale integration
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Summary:In this paper, we propose two methods used in 3-D IC placement that efficiently exploit the die-to-die thermal coupling in the stack. First, through-silicon vias (TSVs) are spread on each die to reduce the local power density and vertically aligned across dies simultaneously to increase thermal conductivity to the heatsink. Second, we move high-power logic cells to the location that has higher conductivity to the heatsink while moving TSVs in the upper dies so that high-power cells are vertically overlapping below the TSVs. These methods are employed in a force-directed 3-D placement successfully and outperform several state-of-the-art placers published in recent literature. We obtain 3-D placement results with shorter routed wirelength at similar temperature. We also obtain 3-D placement results with lower temperatures at similar routed wirelengths.
ISSN:1063-8210
1557-9999
DOI:10.1109/TVLSI.2013.2285593