A 10-Gb/s Low Jitter Single-Loop Clock and Data Recovery Circuit With Rotational Phase Frequency Detector

• Published in: IEEE transactions on circuits and systems. I, Regular papers Regular papers, 2014-11, Vol.61 (11), p.3278-3287
• Main Authors: Fan-Ta Chen, Min-Sheng Kao, Yu-Hao Hsu, Jen-Ming Wu, Ching-Te Chiu, Hsu, Shawn S. H., Chang, Mau-Chung Frank
• Format: Article
• Language: English
• Subjects: Bang-bang phase detector (BBPD); Circuits; clock and data recovery (CDR); Clocks; Data recovery; Electric potential; frequency detector (FD); Frequency locked loops; Image edge detection; Jitter; Locks; Phase frequency detector; Phase locked loops; Phase transformations; Rotational; Semiconductors; Synchronization
• ISSN: 1549-8328; 1558-0806
• DOI: 10.1109/TCSI.2014.2327291

This paper presents a rotational phase frequency detector (RPFD) for reference-less clock and data recovery circuit (CDR). The proposed RPFD changes the bang-bang phase detector (BBPD) characteristic from a bidirectional phase detection to an unilateral phase detection for capturing clock frequency. The phase-and-frequency lock loop (PFLL) locks the clock frequency and the clock phase alternatively. The single-loop CDR replaces the dual-loop CDR so as to eliminate the noise contribution from the frequency lock loop (FLL). This proposed design is fabricated in TSMC mixed-signal 1P9M 90-nm standard CMOS process with overall die size of 0.71- mm 2 . With input 10-Gb/s data of a 2 31 -1 PRBS, the CDR tracks free running clock over the capture range of 1.48 GHz and locks in the acquisition time of 20 μs. At the same time, the peak-to-peak jitters show only 5.0 ps in the recovered clock and exhibits 15.11 ps in the recovered data. The measured chip consumes 92 mW with 1.0-V supply voltage.