Impact of T-gate stem height on parasitic gate delay time in InGaAs-HEMTs

The impact of the stem height of T-gate electrodes on the parasitic gate delay time in InGaAs high electron mobility transistors (HEMTs) is studied. Since T-gates with higher stem height make the parasitic gate capacitance smaller, the higher stem height is expected to minimize the parasitic gate de...

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Bibliographic Details
Published in:Solid-state electronics 2014-12, Vol.102, p.93-97
Main Authors: Yoshida, Tomohiro, Kobayashi, Kengo, Otsuji, Taiichi, Suemitsu, Tetsuya
Format: Article
Language:English
Subjects:
Capacitance
Delay
Delay time analysis
Devices
Drains
Electric potential
Electrodes
Gates
HEMTs
InGaAs
T-gate
Voltage
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Summary:The impact of the stem height of T-gate electrodes on the parasitic gate delay time in InGaAs high electron mobility transistors (HEMTs) is studied. Since T-gates with higher stem height make the parasitic gate capacitance smaller, the higher stem height is expected to minimize the parasitic gate delay. However, a systematic study using the devices with different stem height of T-gates reveals that the parasitic gate delay time decreases with the parasitic gate capacitance only at a drain voltage around the knee voltage and it becomes less sensitive to the parasitic capacitance by the T-gate when the device is operated in the deep saturation region at high drain bias voltage. This result suggests a design strategy for T-gate electrodes so that the tradeoff between the gate resistance and gate capacitance must be considered seriously in the devices for low-voltage applications, while one has more flexibility to use the T-gate electrode with a large head in the devices for high-voltage applications.
ISSN:0038-1101
1879-2405
DOI:10.1016/j.sse.2014.06.005