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A Reconfigurable 50-Mb/s-1 Gb/s Pulse Compression Radar Signal Processor With Offset Calibration in 90-nm CMOS

This paper presents a reconfigurable mixed-signal-processing circuit for high-speed pulse compression radar (PCR). Mixed-signal design techniques incorporate calibration and adaptation to improve the performance of a PCR receiver. Adaptive bandwidth PCR is an important feature for maximizing the dyn...

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Bibliographic Details
Published in:IEEE transactions on microwave theory and techniques 2015-01, Vol.63 (1), p.266-278
Main Authors: Jun Li, Parlak, Mehmet, Mukai, Hirohito, Matsuo, Michiaki, Buckwalter, James F.
Format: Article
Language:English
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Summary:This paper presents a reconfigurable mixed-signal-processing circuit for high-speed pulse compression radar (PCR). Mixed-signal design techniques incorporate calibration and adaptation to improve the performance of a PCR receiver. Adaptive bandwidth PCR is an important feature for maximizing the dynamic range of a low-power radar system. The baseband signal processor includes a variable gain amplifier, 4-bit digital-to-analog converter, high-speed analog correlator, passive integrator, a 4-bit flash analog-to-digital converter, and a multi-range delay-locked loop. This proposed system is fabricated in 90-nm CMOS and can be configured to work from 50 Mb/s to 1 Gb/s with 2/3/5/7-bit Barker codes. The proposed calibration techniques improve the sidelobe reduction to 15.6 dB at 1 Gb/s. The total power consumption is 42 mW at the peak rate of 1 Gb/s for 15-cm range resolution.
ISSN:0018-9480
1557-9670
DOI:10.1109/TMTT.2014.2375177