Power-aware hiding method for S-box protection

A power analysis attack countermeasure, called power-awareness-based hiding, is proposed. It is effective in implementing nonlinear operations, S-boxes, in cryptographic algorithms. An advanced encryption standard (AES) S-box circuit has been implemented in this approach using the Domino logic array...

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Bibliographic Details
Published in:Electronics letters 2014-10, Vol.50 (22), p.1604-1606
Main Authors: Ma, Jiangsha, Li, Xiangyu, Wang, Moyang
Format: Article
Language:English
Subjects:
advanced encryption standard
Arrays
Circuits
Computer simulation
cryptographic algorithms
Cryptography
Delay
Deviation
Domino logic array style
Information and communications
logic arrays
logic design
low‐power electronics
NED
normalised energy deviation
normalised standard deviation
NSD
PAH AES S‐box circuit
PDP
power 3.57 mW
power analysis attack countermeasure
Power consumption
power delay product
power‐aware hiding method
power‐awareness‐based hiding
Standard deviation
synchronisation
S‐box protection
time 1.56 ns
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Description
Summary:A power analysis attack countermeasure, called power-awareness-based hiding, is proposed. It is effective in implementing nonlinear operations, S-boxes, in cryptographic algorithms. An advanced encryption standard (AES) S-box circuit has been implemented in this approach using the Domino logic array style. The post-layout simulation results show that the power-aware hiding AES S-box achieves a delay of 1.56 ns and a mean power consumption of 3.57 mW. The proposed method improves the power delay product by 65%, the normalised energy deviation by 43% and the normalised standard deviation by 30% compared to other secure methods.
ISSN:0013-5194
1350-911X
1350-911X
DOI:10.1049/el.2014.1559