Design and Implementation and On-Chip High-Speed Test of SFQ Half-Precision Floating-Point Adders

• Published in: IEEE transactions on applied superconductivity 2009-06, Vol.19 (3), p.634-639
• Main Authors: Heejoung Park, Yamanashi, Y., Taketomi, K., Yoshikawa, N., Tanaka, M., Obata, K., Ito, Y., Fujimaki, A., Takagi, N., Takagi, K., Nagasawa, S.
• Format: Article
• Language: English
• Subjects: Adders; Applied sciences; Bias; Circuit properties; Circuit simulation; Circuit testing; Circuits; Computer simulation; Design. Technologies. Operation analysis. Testing; Digital circuits; Direct current; Electric, optical and optoelectronic circuits; Electrical engineering. Electrical power engineering; Electromagnets; Electronic circuits; Electronics; Energy consumption; Exact sciences and technology; Floating point arithmetic; Floating-point adder; Format; High speed; Indium tin oxide; Integrated circuit technology; Integrated circuits; Large-scale systems; LSRDP; Niobium; normalizer; Optoelectronic devices; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; SFQ circuits; shifter; Superconducting integrated circuits; System testing; Various equipment and components
• ISSN: 1051-8223; 1558-2515
• DOI: 10.1109/TASC.2009.2019070

We are developing a large-scale reconfigurable data-path (LSRDP) based on single-flux-quantum (SFQ) circuits to establish a fundamental technology for future high-performance computing systems. In the LSRDP, an SFQ floating-point adder (FPA) is one of the main and most complicated circuit blocks. In this paper, we designed and implemented an SFQ half-precision FPA and carried out on-chip high-speed tests. The data format of the half-precision FPA obeys the IEEE standard, in which two input data streams, an 11-bit significand and a 6-bit sign/exponent, are processed bit-serially. The floating-point addition is performed by three steps: (1) alignment and rounding of significands, (2) addition/subtraction of the significands, and (3) normalization of the result. We implemented an SFQ half-precision FPA using the SRL 2.5 kA/cm 2 niobium standard process. The size, power consumption and total junction number are 5.86 mm times 5.72 mm, 3.5 mW and 10224, respectively. The simulated DC bias margin is plusmn20% at 20 GHz operation, which corresponds to the performance of 1 GFLOPS. We successfully confirmed the correct operation of the FPA except a read-out circuit for the significand at 24 GHz by on-chip high-speed tests.