Submission of the first full scale prototype chip for upgraded ATLAS pixel detector at LHC, FE-I4A

A new ATLAS pixel chip FE-I4 is being developed for use in upgraded LHC luminosity environments, including the near-term Insertable B-Layer (IBL) upgrade. FE-I4 is designed in a 130 nm CMOS technology, presenting advantages in terms of radiation tolerance and digital logic density compared to the 0....

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Published in:Nuclear instruments & methods in physics research. Section A, Accelerators, spectrometers, detectors and associated equipment Accelerators, spectrometers, detectors and associated equipment, 2011-09, Vol.650 (1), p.111-114
Main Authors: Barbero, Marlon, Arutinov, David, Beccherle, Roberto, Darbo, Giovanni, Dube, Sourabh, Elledge, David, Fleury, Julien, Fougeron, Denis, Garcia-Sciveres, Maurice, Gensolen, Fabrice, Gnani, Dario, Gromov, Vladimir, Jensen, Frank, Hemperek, Tomasz, Karagounis, Michael, Kluit, Ruud, Kruth, Andre, Mekkaoui, Abderrezak, Menouni, Mohsine, Schipper, Jan David, Wermes, Norbert, Zivkovic, Vladimir
Format: Article
Language:English
Subjects:
Arrays
ATLAS upgrade
Chips
Detectors
Digital
FE-I4
IBL
Integrated circuits
Iron
Pixel detector
Pixels
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Summary:A new ATLAS pixel chip FE-I4 is being developed for use in upgraded LHC luminosity environments, including the near-term Insertable B-Layer (IBL) upgrade. FE-I4 is designed in a 130 nm CMOS technology, presenting advantages in terms of radiation tolerance and digital logic density compared to the 0.25 μ m CMOS technology used for the current ATLAS pixel IC, FE-I3. The FE-I4 architecture is based on an array of 80×336 pixels, each 50 × 250 μ m 2 , consisting of analog and digital sections. In the summer 2010, a first full scale prototype FE-I4A was submitted for an engineering run. This IC features the full scale pixel array as well as the complex periphery of the future full-size FE-I4. The FE-I4A contains also various extra test features which should prove very useful for the chip characterization, but deviate from the needs for standard operation of the final FE-I4 for IBL. In this paper, focus will be brought to the various features implemented in the FE-I4A submission, while also underlining the main differences between the FE-I4A IC and the final FE-I4 as envisioned for IBL.
ISSN:0168-9002
1872-9576
DOI:10.1016/j.nima.2010.11.131