A 400-MHz random-cycle dual-port interleaved DRAM (D super(2)RAM) with standard CMOS Process

This paper describes a standard CMOS process based on embedded DRAM macro with dual-port interleaved DRAM architecture (D super(2)RAM), which is suitable for the leading edge CMOS LSIs with both high-speed and large-scale memories on a chip. This macro exploits three key technologies: fully sense-si...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 2005-01, Vol.40 (5)
Main Authors: Shirahama, M, Agata, Y, Kawasaki, T, Nishihara, R, Abe, W, Kuroda, N, Sadakata, H, Uchikoba, T, Takahashi, K, Egashira, K, Honda, S, Miura, Miho, Hashimoto, S, Kikukawa, H, Yamauchi, H
Format: Article
Language:English
Subjects:
Breakdown
Capacitors
Circuits
CMOS
Dynamic random access memory
High speed
Leading edges
Online Access:Get full text
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Summary:This paper describes a standard CMOS process based on embedded DRAM macro with dual-port interleaved DRAM architecture (D super(2)RAM), which is suitable for the leading edge CMOS LSIs with both high-speed and large-scale memories on a chip. This macro exploits three key technologies: fully sense-signal-loss compensating technology based on the whole detailed noise element breakdowns, the novel striped trench capacitor (STC) cell, and the write-before-sensing (WBS) circuit by decoded write-bus. A 400-MHz random cycle access has been verified for D super(2)RAM fabricated by a 0.15- mu m standard CMOS process.
ISSN:0018-9200
DOI:10.1109/JSSC.2005.845995